Currently state-of the-art integrated circuits (ICs), such as microprocessors, are designed with hundreds of millions of transistors. A microprocessor's performance is largely determined by the input clock speed. Internal clock signals generated from the input clock coordinate data transfers between circuit components. However, microprocessor designers continue to increase clock frequencies which reduce timing budgets to meet internal setup and hold times.
Typically, during design of an IC a clock-tree is generated and used to distribute a clock signal from a common source to various circuit components. A typical design flow proceeds from design synthesis to place and route and then to clock-tree synthesis (CTS). However, CTS is unaware of the logic-interaction and timing requirements between various circuit elements, and there is a possibility of high clock divergence between interacting circuit elements, which may heavily impact performance and cause race (hold) conditions during circuit operation.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items.